Linköping Studies in Science and Technology
Dissertation No. 414
RT Level Testability Improvement by
Testability Analysis and Transformations
som för avläggande av teknisk doktorsexamen vid Linköpings universitet kommer att offentligt
försvaras i seminarierum Belöningen, Hus B, 1 tr, Linköpings universitet, fredagen den 26 januari
1996, kl 13.15.
An important concern in VLSI design is how to make the manufactured circuits more testable.
Current design tools exploit existing design for testabfiity (DFT) techniques to improve design
testability in the post design phase. Since the testability improvement may affect design
performance and area, re-designing is often required when performance and area constraints are not
satisfied. Thus design costs and time to bring a product to the market are all increased. This
dissertation presents an approach to improving design testability during an early design stage, at
register-transfer (RT) level, to overcome these disadvantages. It improves testabilty by three
methods under the guidance of a testability analysis algorithm.
The proposed RT level testability analysis algorithm detects hard-to-test design parts by
taking into account the structures of a design, the depth from I/0 ports and the testability
characteristics of the components used. It reflects the test generation complexity and test application
time for achieving high test quality.
The first testability improvement method uses the partial scan technique to transform hard-to-
test registers and lines to scan registers and test modules. Design testability is increased by direct
access to these hard-to-test parts.
The second method uses DFT techniques to transform hard-to-test registers and lines into
partitioning boundaries, so that a design is partitioned into several sub-designs and their boundaries
become directly accessible. Since test generation can be carried out for each partition independently,
test generation complexity is significantly reduced. Also the test generation results can be shared
arnong the partitions.
The third method improves the testability by enhancing the state reachability of the control
part of a design. It analyzes the state reachability for each state in the control part. The state
reachability enhancements are motivated by 1) controlling the termination of feedback loops, 2)
increasing the ability of setting and initialling registers and the control of test starting points, and 3)
enabling arbitrary election of conditional branches.
Experiments using commercial tools and test benchmarks are performed to verify our
approaches. Results show the efficiency of the test quality improvement by using our testability
This work has been supported by the Swedish National Board for Industrial and Technical Development
Department of Computer and Information Science
S-581 83 Linköping
ISBN 91-7871-654-3 ISSN 0345-7524